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| application note easy application design with the l4970a, monolithic dc-dc converters family by g. gattavari and c. diazzi the technology the technology architecture is based on the verti- cal dmos silicon gate process that allows a channel length of 1.5 micron ; using a junction isolation technique it has been possible to mix on the same chip bipolar and cmos transistors along with the dmos power components (fig. 2). figure 1 shows how this process brings a rapid increase in power ic complexity compared to conventional bipolar technology. in the 70's class b circuits and dc circuits al- lowed output power in the range of 70w. by 1980, with the introduction of switching tech- niques in power ics, output powers up to 200w were reached ; with bcd technology the output power increased up to 400w. AN557/1297 the l497xa series of high current switching regulator ics exploit multipower-bcd technology to achieve very high output currents with low power dissipation up to 10a in the multiwatt power package and 3.5a in a dip package . 1/47
the step-down configuration fig. 3 shows the simplified block diagram of the circuit realizing the step-down configuration. this circuit operates as follows : q1 acts as a switch at the frequency f and the on and off times are suitably controlled by the pulse width modulator circuit. when q1 is saturated, energy is absorbed from the input which is transferred to the output through l. the emitter voltage of q1, v e , is vi- vsat when q is on and -v f ( with v f the forward voltage across the d diode as indicated) when q1 is off. during this second phase the current cir- culates again through l and d. consequently a rectangular shaped voltage appears on the emit- ter of q1 and this is then filtered by the l-c-d net- work and converted into a continuous mean value across the capacitor c and therefore across the load. the current through l consists of a continu- ous component, i load , and a triangular-shaped component super-imposed on it, d i l , due to the voltage across l. figure 1: bcd process and increase in power ics complexity. figure 2: cross section of the bcd mixed technology. application note 2/47 fig. 4 shows the behaviour of the most significant waveforms, in different points of the circuit, which help to understand better the operation of the power section of the switching regulator. for the sake of simplicity, the series resistance of the coil has been neglected. fig. 2a shows the behaviour of the emitter voltage (which is practically the volt- age across the recirculation diode), where the power saturation and the forward v f drop across the diode era taken into account. the on and off times are established by the fol- lowing expression : v o =( v i - v sat ) t on t on + t off fig. 4b shows the current across the switching transistor. the current shape is trapezoidal and the operation is in continuous mode. at this stage, the phenomena due to the catch diode, that we consider as dynamically ideal, are neglected. fig. 4c shows the current circulating in the recircula- tion diode. the sum of the currents circulating in the power and in the diode is the current circulat- ing in the coil as shown in fig. 4e. in balanced conditions the d i l + current increase occuring dur- ing t on has to be equal to the d i l decrease oc- curring during t off . the mean value of i l corre- sponds to the charge current. the current ripple is given by the following for- mula : d il + =d il - = ( v i - v sat ) - v o l t on = v o + v f l t off it is a good rule to respect to io min i l /2 relation- ship, that implies good operation in continuous mode. when this is not done, the regulator starts operating in discontinuous mode. this operation is still safe but variations of the switching fre- quency may occur and the output regulation de- creases. fig. 4d shows the behaviourof the voltage across coil l. in balanced conditions, the mean value of the voltage across the coil is zero. fig. 4f shows the current flowing through the capacitor, which is the difference between i l and i load . in balanced conditions, the mean current is equal to zero, and d i c = d i l . the current i c through the capacitor gives rise to the voltage ripple. this ripple consists of two components : a capaci- tive component, d v c , and a resistive component, d v esr , due to the esr equivalent series resis- tance of the capacitor. fig. 4g shows the capaci- tive component d v c of the voltage ripple, which is the integral of a triangular-shaped current as a function of time. moreover, it should be observed that v c (t) is in quadrature with i c (t) and therefore with the voltage v esr . the quantity of charge d q + supplied to the capacitor is given by the area en- closed by the abc triangle in fig. 4f : figure 3: the basic step-down switching regulator configuration application note 3/47 figure 4: principal circuit waveforms of the figure 1 circuit. application note 4/47 d q = 1 2 ? t 2 ? d i l 2 which therefore gives: d v c = q c = d i l 8fc fig. 4h shows the voltage ripple v esr due to the resistive component of the capacitor. this compo- nent is v esr (t) = i c (t) ? esr. fig. 4i shows the overall ripple v o , which is the sum of the two pre- vious components. as the frequency increases (> 20khz), which is required to reduce both the cost and the sizes of l and c, the v esr component becomes dominant. often it is necessary to use capacitors with greater capacitance (or more ca- pacitors connected in parallel to limit the value of esr within the required level. we will now examine the stepdown configuration in more detail, referring to fig. 1 and taking the be- haviour shown in fig. 4 into account. starting from the initial conditions, where q = on, v c =v o and i l =i d = 0, using kirckoff second prin- ciple we may write the following expression : v i =v l +v c (v sat is neglected against v i ). v i = l d il dt + v c = l d il dt + v o (1) which gives : d il dt = ( v i - v o ) l (2) the current through the inductance is given by : i l = ( v i - v o ) l (3) when v i ,v o , and l are constant, i l varies linearly with t. therefore, it follows that : d i l + = ( v i - v o ) t on l (4) when q is off the current through the coil has reached its maximum value, i peak and because it cannot very instantaneously, the voltage across the ased to allow the recirculation of the current through the load. when q switches off, the following situation is present : v c (t) = v o ,i l (t) = i d (t) = i peak and the equation associated to the following loop may be written : v f + l d il dt + v c = 0 (5) where : v c =v o di l dt =- ( v f + v o ) / l (6) it follows therefore that : i l ( t )=- v f + v o t t (7) the negative sign may be interpretated with the fact that the current is now decreasing. assuming that v f may be neglected against v o , during the off time the following behaviour occurs : i l = v o l t (8) therefore : d i l + = v o l t off (9) but, because d i l + = d i l if follows that : ( v i - v o ) t on l = v o t off l which allows us to calculate v o : v o = v i t on t on t off = v i t on t (10) where t is the switching period. expression (10) links the output voltage v o to the input voltage v i and to the duty cycle. the rela- tion-ship between the currents is the following : i idc = io dc ? t on t efficiency the system efficiency is expressed by the follow- ing formula : h % = p o p i ? 100 where p o =v o i o (with i o =i load ) is the output power to the load and p i is the input power absorbed by the system. p i is given by p o , application note 5/47 plus all the other system losses. the expression of the efficiency becomes therefore the following : h= p o p o + p sat + p d + p l + p q + p sw (12) dc losses p sat :saturation losses of the power transistor q. these losses increase as v i decreases. p sat = v sat ? i o t on t + v sat i o v o v i (13) where t on t = v o v i and v sat is the power transistor saturation at current io. p d : losses due to the recirculation diode. these losses increase as v i increases, as in this case the on time of the diode is greater. p d = v f i o v i - v o v i = v f i o ( 1 - v o v i ) (14) where v f is the forward voltage of the recircula- tion diode at current i o . p l : losses due to the series resistance r s of the coil p l =r s i o 2 (15) p q : losses due to the stand-by current and to the power driving current : p q =v i i q , (16) in which iq is the operating supply current at the operating switching frequency. iq includes the oscillator current. switching losses p sw :switching losses of the power transistor : p sw =v i i o t r + t f 2t the switching losses of the recirculation diode are neglected (which are anyway negligible) as it is assumed that diode is used with recovery time much smaller than the rise time of the power tran- sistor. we can neglect losses in the coil (it is assumed that d i l is very small compared to i o ) and in the output capacitor, which is assumed to show a low esr. calculation of the inductance value, l calculation t on and t off through (4) and (9) re- spectively it follows that : t on = d i l + ? l v i - v o t off = d i l - ? l v o but because : t on +t off = t and d i l + = d i l = d i l , it follows that : t on = d i l ? l v i - v o + d i l ? l v o = t (17) calculating l, the previous relation becomes : l = ( v i - v o ) v o v i d i l t (18) fixing the current ripple in the coil required by the design (for instance 30% of i o ), and introducing the frequency instead of the period, it follows that : l = ( v i - v o ) v o v i ? 0.3 ? i o ? f where l is in henry and f in hz calculation of the output capacitor c from the output node in fig. 3 it may be seen that the current through the output capacitor is given by : i c (t) = i l (t) i o figure 5: equivalent circuit showing recirculation when q1 is turned off. application note 6/47 from the behaviour shown in fig. 4 it may be cal- culated that the charge current of the output ca- pacitor, within a period, is d i l /4, which is supplied for a time t/2. it follows therefore that : d v c = d i l 4c t 2 = d i l t 8c = d i l 8fc (19) but, remembering expression (4) : d i l + =( v i - v o ) t on l and t on = v o v i t therefore equation (19) becomes : d v c = ( v i - v o ) v o 8v i f 2 l c finally, calculating c it follows that : c = ( v i - v o ) v o 8v i d v c f 2 l (20) where : l is in henrys c is in farads fisinhz finally, the following expression should be true : esr max = d v cmax d i l (21) it may happen that to satisfy relation (21) a ca- pacitance value much greater than the value cal- culated through (20) must be used. transient response sudden variations of the load current give rise to overvoltages and undervoltages on the output voltage. since i c = c (dv c /dt) (22), where dv c = d v o , the instantaneous variation of the load cur- rent d i o is supplied during the transient by the output capacitor. during the transient, also cur- rent through the coil tends to change its value. moreover, the following is true : v l = l di l dt (23) where di l = d i o v l =v i v o for a load increase v l =v o for a load decrease calculating dt from (22) and (23) and equalizing, it follows that : l di l v l = c dv c i c calculating dv c and equalizing it to d v o , it follows that : d v o = l d i o 2 c ( v i - v o ) (24) for + d i o d v o = l d i o 2 cv o (25) for - d i o from these two expressions the dependence of overshoots and undershoots on the l and c val- ues may be observed. to minimize d v o it is there- fore necessary to reduce the inductance value l and to increase the capacitance value c. should other auxiliary functions be required in the circuit like reset or crowbar protections and very variable loads may be present, it is worthwhile to take spe- cial care for minimizing these overshoots, which could cause spurious operation of the crowbar, and the under-shoot, which could trigger the reset function. device description for a better understanding of how the device functions, a description will be given of the princi- ple blocks that compose the device. the block diagram of the device is shown in fig.6 power supply the device contains a stabilized regulator (vstart = 12v) that provides power to the analogic and digital control blocks as well as the section of the bootstrap. the vstart voltage also powers the blocks that operates the internal reference volt- age of 5.1v, with a precision of +2%, necessary for the feedback. oscillator, sync. and voltage feed- forward functions the oscillator block generates a sawtooh wave signal that sets the switching frequency of the system. this signal, compared with the output voltage of the error amplifier, generates the pwm signal that will then sent to the power output stage. the oscillator also contains the voltage feedforward function that, being completely inte- grated, does not require additional external com- ponents to function. the vff function operates with supply voltages from 15v to 45v. the d v/ d t of the sawtooh is directly proportional to the sup- ply voltage vi. as vi increases, the conduction time (ton) of the power transistor decreases in such way as to pro- vide to the coil, and therefore to the load, the product volt x sec constant. application note 7/47 fig. 7 shows the duty-cycle varies as a result of the changes in slope of the ramp with the input voltage vi. the output of the error amplifier should not change to maintain the output voltage in regulation. this function allows for the increase of speed in response to the rapid change of the supply voltage and for a greatly reduced ouput ripple at the mains frequency. in fact, the slope of the ramp is modulated by the ripple, generally present in the order of several volts on the input of the regulator, particularly when the solution with a mains transformer is used. fig. 8 shows the simplified electrical diagram of the oscillator. a resistor, connected between the rosc pin and gnd, sets the current that is internally reflected in the pin cosc, in order to charge the external ca- pacitor to which it is connected. the voltage to the rosc pin is not fixed, but is tied to the instan- taneous value of vi; this is needed to achieve the feedforward voltage function, in which the slope of the ramp is directly proportional to the supply voltage. a comparator senses the voltage at the cosc capacitor. when the voltage reaches the value present at the inverting input of the compa- rator, the output from the comparator goes high and is sent to the two transistors q1 and q2. q1 is responsible for discharging the external cosc capacitor with a current of approx. 20ma, while q2 imposes at the inverted input of the comparator a voltage of 2vbe (approx. 1.3v) that is the low-threshold of the ramp. some useful for- mulas for calculating the various parameters of the oscillator block are: figure 6: block diagram of the 10a monolithic regulator l4970a. v2 v7 d93in006 vi=30v vi=15v vc t vi=30v vi=15v t figure 7: voltage feeforward waveform. application note 8/47 1) oscillator charge current: i charge = v i - 9v be r osc (for 15v < vi < 45v) 2) oscillator discharge current: i disch = 20ma 3) peak voltage ramp: v th - h = v i - 9v be rosc + 2v be this formula is obtained in the following way: indi- cating with ve the voltage of the emitter of the npn transistor connected to vcc, and v- the voltage at the inverted input of the comparator, one has: (a) v e = v i 3 - v be (b) v - = ? ? ? v e - 2v be 3r ? r ? ? ? + 2v be by substituting (a) into (b), one obtains: v - = ( v i 3 - v be )- 2v be 3 + 2v be = v i - 9v be 9 + 2v be 4) valley voltage ramp: v th-l =2 vbe 5) switching frequency: f sw = 9 r osc c osc it should be noted that formula (5) does not take into account the discharge time of cosc which cannot be neglected when one is working at fre- quencies equal or higher than 200khz. the dis- charge time is also tied to the value of cosc itself. analitycally one has: 6) t disch = v th - h - v th - l 20ma ? c osc from which is obtained the more closely approxi- mate expression of the oscillator frequency: 7) f sw = 1 r osc ? c osc 9 + t disch during the discharge time of cosc, a clock pulse is generated internally that is made subsequently available on the sync. pin and that can be used to synchronize other regulators. (3 devices of the same family maximum). the sync. pulse generated has a typical range of 4.5v and the current avail- ability is 4.5ma. in general, it is better that the sync pulse is at least 300-400ns in order to be able to synchronize a range of existing regulators; to obtain this result, values of suggested capacitors, in differ- ent test circuits, have been selected. the typical duration of the synchronizing pulse with the sug- gested values of cosc are as follows: l497x family (multiwatt package) c osc (nf) - r osc = 16k w sync (ns) 0.68 1 1.2 1.5 2.2 3.3 4.7 140 230 270 330 450 680 1100 l497x family (powerdip package) c osc (nf) - r osc = 30k w sync (ns) 1.2 1.5 2.2 3.3 4.7 230 280 420 600 900 vi 2r 13 2r r rosc cosc pwm comp. q1 r q2 clock d93in007 - + figure 8: oscillator circuit. application note 9/47 obviously, synchronize pulses of eccessive dura- tion can greatly reduce the max duty-cycle and produce distortions in the sawtooth of the syn- chronized regulator working as slave. p.w.m. comparing the sawtooth signal generated by the oscillator and the output of the error amplifier, generates the pwm signal which is sent to the driver of the output power stage. the pwm sig- nal, in the path towards the output stage, also en- counters a latch block to prevent other pulses from being sent at same period to the output, possibly damaging the power stage. in the pwm block, a duty-cycle limiter has also been intro- duced. such a limiter is obtained by taking advan- tage of the synchronizing pulse generated, the power output stage is inhibited. even if the error amplifier gives a large signal to the peak of the ramp, the power stage will not be able to operate in dc, but will be switched off at each clock pulse. the max. obtainable duty-cycle is higher than 90%; this, however depends on the working fre- quency and the value of cosc. using the formulas 6) and 7) a precise calculation can be done. soft start the soft start function is essential for a correct startup of the device and for an output voltage that, at the switch on, increases in a monotonous mode without dangerous output overvoltages and without overstress for the power stage. soft start operates at the startup of the system and after an intervention of the thermal protection. fig. 9 shows the simplified diagram of the startup functions. the function is carried out by means of an external capacitor connected to the soft start pin, which is charged with a constant current of about 100 m a to a value of around 7v. during the charging time, the output of the error transcon- ductance amplifier, because of q1, is forced to in- crease at the same rising edge time of the exter- nal softstart capacitor css. clamped error amplifier output vc output current soft start time t d93in011 t figure 10: soft start waveforms. figure 9: soft start circuit. application note 10/47 the pwm signal begins to be generated as soon as the output voltage of the error amplifier crosses the ramp; at this point the output stage begins to commutate, slowly increasing its on time (see fig. 10). the charge of the css capacitor, as already men- tioned, begins each time the device is supplied with power and after which an anomalous condi- tion is created, as the intervention of thermal pro- tection or of the undervoltage lockout. calculating the duty-cycle and soft- start time let us suppose that the discharge time of the os- cillator capacitor, cosc, is neglected. this is an approx. valid for switching frequencies up to 200khz. let us indicate with vr the output voltage of the error amplifier, and with vc the voltage of the oscillator ramp. the pwm comparator block commutates when vr = vc. therefore: 8) v r = v c = v pp t ? t = v i - 9v be 9 ? t ? t from which is obtained 9) t = v r ? t ? ( v i - 9v be ) 9 the time t obtained from this equation is equal to the on time of the power transistor. the corre- sponding duty-cycle is given by: 10) d = t on t = v r ? t ? ( v i - 9v be ) 9t = v r ? ( v i - 9v be ) 9 = v o v i consequently, after leaving the discharged ca- pacitor of soft start, the output of the regulator will reach its value when the voltage across the css capacitor, charged with constant current, has reached the value vr - 0.5v. the time necessary in order that the output rises from zero to the nominal value is given by: 11) t start - up = c ss ? ( v r - 0.5v ) i ss in which css is the soft start capacitor and iss the soft start current. considering soft start time as tss, the required time for the soft start capaci- tor to change itself approx from (2vbe - 0.5v) = (1.2v - 0.5v) to vr - 0.5v, is: 12) t ss = c ss ? ( v r - 1.2v ) i ss by taking vr from (10): 13) v r = v o v i ? 9 v i - 9v be and substituting it in (12), we obtain: 14) t ss = c ss i ss ? ? ? v o v i ? 9 v i - 9v be - 1.2v ? ? ? undervoltage lockout the device contains the protection block of under- voltage lockout which keeps the power stage turned-off as long as the supply voltage does not reach at least 12v. at this point the device starts up with soft start. the function of undervoltage is also provided with an hysteresis of 1v to make it better immune to the ripple present on the supply voltage. error amplifier the error amplifier is a transconductance type and deliver an output current proportional to the voltage inbalance of the two inputs. the simplified diagram is presented in fig 12.the principal char- acteristics of this uncompensated operational am- plifier are the following: gm = 4ma/v, ro = 2.5mohm, avo = 80db, isource-sink = 200ua, input bias current = 0.3ua. the frequency response of the op. amp. is given in fig. 13. ignoring the high frequency response and hy- pothesizing that the second pole is below the 0 db axis in the all the conditions of loop compen- sation, it is possible to make a first approximation with the equivalent circuit of fig. 14 figure 11: soft sart time waveform. application note 11/47 in which: 15) av ( s ) = gm ? r o 1 + sr o c o where c o = 3pf the error amplifier can be easily compensated thanks to the high output impedance (see fig. 14) the resulting transfer function is as in the follow- ing: (16) av ( s ) = gm ? r o ? ( 1 + src cc ) s 2 r o c o r c c c + s ( r o c c + r o c o + r c c c )+ 1 the bode diagram is shown in fig.16. the compensation circuit introduces a pole at low frequency and a zero that is generally calculated to be put in the proximity of the resonance fre- quency of the output lc filter. the second pole at high frequency generally falls in a zone of no interest (for the system stability, one must consider the zero introduced by esr figure 12: error amplifier circuit. figure 13: open loop gain (error amplifier only) figure 14: error amplifier equivalent circuit. figure 15: compensation network of the error amplifier figure 16: bode plot showing gain and phase of compensated error amplifier application note 12/47 characteristic of the output capacitor. not all the designers agree on this solution). if necessary, however, one can turn to more so- phisticated compensation circuitry. an example is shown in fig. 17. such a circuit introduces a pole at low-frequency and two zeros. 17) z1 = 1 2 p r1 c1 z2 = 1 2 p r2 c2 it must be remembered, however, that because of the high output impedance of the error amplifier, a second pole is also present: 18) p2 = gm 2 p c1 we normally suggest a high value for r1 to re- duce the value of the capacitor c1 and allocate the pole p2 at the highest possible frequency. the essential limitation to the max value of r1 is the offset introduced by the input bias current of the error amplifier. in the case of output voltage regulated higher than 5.1v, an external divider should be introduced. it's than possible to intro- duce a second zero using the following network: two zeros and two poles are introduced: 19) z1 = 1 2 p r o c c z2 = 1 2 p r1 c1 p1 = 1 2 p r o c c p2 = 1 2 p rx c1 where rx = r1 ? r2 r1 + r2 application example consider the block diagram of fig. 19, repre- senting the internal control loop section, with the application values: fswitch = 200khz, l = 100 m h, c = 1000 m f, po = 50w, vo = 5.1v, io = 10a and fo = 500hz. g loop = pwm ? filter the system requires that dc gain is maximum to achieve good accuracy and line rejection. beyond this a bandwidth of some khz is usually required for a good load transient response. the error am- plifier transfer function must guarantee the above constrainst. a compensation network that could be used is shown in fig. 21. a ( s )= ( 1 + sr1 c1 )( 1 + sr2 c2 ) sr1 c1 ( 1 + s c1 gm ) figure 17: one pole, two zero compensation network figure 18: compensation network for output voltages higher than 5.1v figure 19: block diagram used in stability calculation figure 20: frequency behaviour of the circuit of fig. 19 application note 13/47 the criterium is to define z1, z2 close to the reso- nant pole of the output lc filter. the gm/2 p c1 pole must be placed at a frequency at which open loop gain is below 0db axis (fig. 22). current limiting a complete regulation system will be equipped with a good current limiter able to protect from load breaking and operator error controlls. the current limiting function is totally integrated and does not require any external component. the output current is sensed by an internal low- value resistor, in series with the drain of the dmos vertical power transistor.. a precision current limitation of 10% relative at the peak current is guaranted. during overcurrent situation the pulse by pulse current limitation pro- duce an output stage switching frequency reduc- tion. the block diagram of the current limiting is shown in fig. 23. figure 21: compensation network. acsj gloop pwm+filter 50hz 500hz 5kz 50khz 20 40 db d93in012 figure 22: bode plot of the regulation loop with the compensation network of fig. 21. figure 23: current protection circuit. application note 14/47 in overcurrent situation the comparator send a signal at the flip-flop set input, an inhibit pulse is immediatly generated from it and sended at the output stage switching off the power mos. a reset pulse input in generated from an 40khz internal oscillator. after the first reset pulse the control loop will start to regulate the system an the output current will increase following the principal oscillator fre- quency. if overcurrent condition is still present the current limiting will be activate again. this type of current limiting ensure a constant output current in overload or short circuit condi- tion and allow a good reliability at high frequency (500khz) reducing the problems relative at the in- ternal signal delay through the protection blocks. the inductor current in overload condition in shown in fig. 24. the 40khz internal oscillator is synchronized with the principal one. if the system work with a oscil- lator tracks the principal oscillator frequency. in this way the switching frequency will not increase in overload situation. a particular care has to be taken in the inductor value in order to avoid problems during overload or short circuit conditions. a critical situation is present with high switching frequency, (more than 200khz) where a small inductor value is used and with high capacitive load. in order to return in nominal condition after a short circuit the inductor ripple at 40khz with the nominal output voltage and current has to be lower than the current limitation value. example let us consider l4970a, 10a. (the same ap- proach can be used for all the family). the inductor ripple current is given by the follow- ing formula: d i l = ( v i - v o ) ? v o v i ? fsw ? l where fsw = 40khz 10% in order to get the maximum inductor ripple cur- rent, the previous formula becomes: d i l = ( v imax - v omax ) ? v omax v imax ? f sw min ? l the current limitation for l4970a will start to work at 13a. therefore: i lim min >i onom + d i l 2 where i onom = 10a for l4970a. power fail-reset circuit the l4970a include a voltage sensing circuit that may be used to generate a power on power off reset signal for a microprocessor system. the cir- cuit senses the input supply voltage and the out- put generated voltage and will generate the re- quired reset signal only when both the sensed voltages have reached the required value for cor- rect system operation. the reset signal is gener- ated after a delay time programmable by an ex- ternal capacitor on the delay pin. fig 25 shows the circuit implementation of reset circuit. the supply voltage is sensed on an external pin, for programmability of the threshold, by a first com- parator. the second comparator has the refer- ence threshold set at slightly less the ref. voltage for the regulation circuit and the other input con- nected internally at the feedback point on the regulated voltage. when both the supply voltage and the regulated voltage are in the correct range, transistor q1 turns off and allows the cur- rent generator to charge the delay capacitor dis- charges completely before initialization of a new reset cycle. the output gate assures immediate take of reset signal without waiting for complete discharge of delay capacitor. reset output is an open collector transistor capable of sinking 20ma at 200mv voltage. fig 26 shows reset waveforms. figure 24: overload inductance current. application note 15/47 figure 25: power fail and reset circuit. vi rising p.fail threshold turn-on threshold 11v falling p.fail threshold turn-off threshold 10v t 5.1v 100mv histeresis 4.9v 5v falling reset threshold vo=5.1v rising reset threshold output reset tdr tdr t t t delay reset power fail time d93in013 figure 26: reset and power fail and reset circuit. application note 16/47 power stage the simplified diagram of the output stage is shown in the fig. 27. the power stage and the circuit connected with it are by far the most important and critical compo- nents when one wants to obtain good perform- ance at high switching frequency. the power transistor must have excellent charac- teristics from the point of view of both the switch- ing speed and the robustness. the transistor dmos, with its intrinsic charac- teristics of elevated speed, no second breakdown phenomenom and easy driving proves to be par- ticularly suitable for this type of application that normally works at high frequency. for a properly driving of the dmos gate it is nec- essary to use an external bootstrap capacitor. when the voltage vs is low the cboot capacitor is charged through the internal diode d1, at the value of voltage equal to that of vstart, which is about 12v; the next step oversees that q3 is turned off, q2 is driven in gate by q1 so that q1 can go in saturation, and its source can go up rise towards vi. cboot maintains its charge and guarantees a volt- age equal vi+12v at the gate of q7, so that can enter into region of low resistance. at this point the diode d1 turns on to be inversely polarized, disconnecting the 12v section from that of the driving power stage. when q2 is on the driven current of the power stage requires from the bootstrap capacitor a typi- cal current of 400ua. when q2 is off a current of 2.5ma is required to mantain q2 in that state. this current however is not delivered from the bootstrap capacitor, but rather from the internal regulator of 12v, while the output current flowing in the freewheeling diode. the circuit described is capable of obtaining com- mutation, rise and fall time, a typical value of 50ns. in principle, it would have been feasible to reduce furthermore the commutation time whithout any reliability problems. this was not believed to be advantageoussince it would not have been of any benefit if one thinks of the trr time of the catch diode (with trise of 50ns also the schottky diodes begin to show limi- tations) and of the conseguent increase of differ- ent disturbances caused bt too higly elevated di/dt. ther following table shows the main features of the dmos transistor. figure 27: power stage circuit. figure 28: gate-charge curve for the power application note 17/47 thermal shutdown the thermal protection intervenes when the junc- tion temperature reaches 150 o c; it intervenes di- rectly on the output stage turning it off quikly and in the meantime discharging the soft start capaci- tor. the reference voltage and the oscillator will con- tinue to work regularly. the thermal shutdown has a hysteresis, after its intervention, it is necessary to wait for the junction temperature to lower around 30 o c before the de- vice will begin to work properly again. the device restart to work by using the soft start function. table 1. b vdss > 60v at i d = 1ma v gs =0v r ds(on) = 100m w at i d = 10a t j =25 cv gs = 10v r ds(on) = 150m w at i d = 10a t j = 150 cv gs = 10v v th =3v ati d = 1ma table 2: high current switching regulator ics. parameter l497x family l4970a l4977a l4975a l4974a l4972a l4972ad surf. mount. max. input operating voltage 50v 50v 50v 50v 50v 50v output voltage range 5.1v ( 2%) to 40v max. output current 10a 7a 5a 3.5a 2a 2a power switch r dson at 25 c 0.13 w typ. switching mode control system continuous mode, direct duty cycle control with voltage feed-forward max. switching freq. 500khz 500khz 500khz 200khz 200khz 200khz efficiency v input = 35v v out = 5.1v 10a 80% at 200khz 7a 80% at 200khz 5a 85% at 200khz 3.5a 85% at 100khz 2a 85% at 100khz 2a 85% at 100khz current limiting constant current soft start yes reset and power fail yes synch yes crowbar no package max. r th j-case (pin) r th j-amb multiwatt15 1 c/w 35 c/w multiwatt15 1 c/w 35 c/w multiwatt15 1 c/w 35 c/w powerdip 16+2+2 12 c/w 60 c/w powerdip 16+2+2 12 c/w 60 c/w so20l 6 c/w 80 c/w application note 18/47 applications even though the regulators of the l4970a family has been designed to work only in step down configuration we will see next how these regula- tors can be use in large range of applications. in same cases the l4970a device will be used as an example for the entire family assembled in multiwatt package and the l4974a will be used for the types in powerdip package. anyway the suggested applications can be ex- tended to any other device of the family by adjust- ing if necessary the external components using the given equation for the calculation. typical application the fig. 29 shows the electrical diagram of the typical application, complete with all the auxiliary functions. the same application suggested in the data sheet as test circuit and is the same used for the final dynamic test. all our devices are 100% tested both in static and dynamic conditions. included in the dynamic test are obviously the ex- ternal components: the coil, catch diode and out- put capacitor which have been defined for all regulators. shown below are the electrical diagrams of 5 de- vices that compose the family of this regulator complete with the value of the external compo- nents and with the relative pcb layout. output voltages higher than 5.1v are possible us- ing an output resistive divider. for v o > 24v, for safety reasons it must be avoided the zero load condition. in the application with high current, connected to the output divider are added two other resistances that permit the separation of sensing and forcing, in such way as to compen- sate the fall of voltage on the connecting cables between the output and the load. connecting directly the output to the feedback pin a 5.1v 2% is obtained. the following table can be help for a rapid calculation of a resistor divider to obtain some of the most standard output volt- age. figure 29: l4970a typical application circuit. application note 19/47 figure 30: test and evaluation board circuit typical performances (using evaluation board) : n = 83% (v i = 35v ; v o =v ref ;i o = 10a ; f sw = 200khz) v o ripple = 30mv (at 10a) with output filter capacitor esr 60m w line regulation = 5mv (v i = 15 to 50v) load regulation = 15mv (i o = 2 to 10a) for component values, refer to test circuit part list. parts list r 1 = 30k w c 1 ,c 2 = 3300 m f 63v l eyf (roe r 2 = 10k w c 3 ,c 4 ,c 5 ,c 6 = 2.2 m f r 3 = 15k w c 7 = 390pf film r 4 = 16k w c 8 = 22nf mkt 1817 (ero) r 5 =22 w 0,5w r 6 = 4k7 c 9 = 2.2nf kp1830 r 7 =10 w c 10 = 220nf mkt r 8 = see tab. a c 11 = 2.2nf mp1830 r 9 = option **c 12 ,c 13 ,c 14 = 220 m f 40v l ekr r 10 = 4k7 c 15 =1 m f film r 11 =10 w d1 = mbr 1560ct (or 16a/60v or equivalent) l1 = 40 m h core 58071 magnetics 27 turns 1,3mm (awg 16) cogema 949178 * 2 capacitors in parallel to increase input rms current capability ** 3 capacitors in parallel to reduce total output esr table b suggested bootstrap capacitors operating frequency bootstrap cap.c10 f = 20khz 680nf f = 50khz 470nf f = 100khz 330nf f = 200khz 220nf f = 500khz 100nf table a. v0 r10 r8 12v 15v 18v 24v 4.7k w 4.7k w 4.7k w 4.7k w 6.2k w 9.1k w 12k w 18k w application note 20/47 figure 31: p.c. board (back side) and components layout of the circuit of fig. 30. (1:1 scale) figure 32: p.c. board (back side) and components layout of the circuit of fig. 30. (1:1 scale) application note 21/47 figure 33: test and evaluation board circuit. typical performances (using evaluation board) : n = 83% (v i = 35v ; v o =v ref ;i o =2a;f sw = 100khz) v o ripple = 30mv (at 1a) line regulation = 12mv (v i = 15 to 50v) load regulation = 7mv (i o = 0.5 to 2a) for component values refer to the fig. 32 (part list). part list r 1 = 30k w r 2 = 10k w r 3 = 15k w r 4 = 30k w r 5 =22 w r 6 = 4.7k w r 7 = see table a r 8 = option *c 1 =c 2 = 1000 m f 63v eyf (roe) c 3 =c 4 =c 5 =c 6 = 2,2 m f 50v c 7 = 390pf film c 8 = 22nf mkt 1837 (ero) c 9 = 2.7nf kp 1830 (ero) c 10 = 0.33 m f film c 11 = 1nf ** c 12 =c 13 =c 14 = 100 m f 40v ekr (roe) c 15 =1 m f film d1 = sb 560 (or equivalent) l1 = 150 m h core 58310 magnetics 45 turns 0.91mm (awg 19) cogema 949181 * 2 capacitors in parallel to increase input rms current capability. * * 3 capacitors in parallel to reduce total output esr. table b suggested boostrap capacitors operating frequency boostrap cap.c10 f = 20khz 680nf f = 50khz 470nf f = 100khz 330nf f = 200khz 220nf f = 500khz 100nf table a. v0 r10 r8 12v 15v 18v 24v 4.7k w 4.7k w 4.7k w 4.7k w 6.2k w 9.1k w 12k w 18k w note: in the test and application circuit for l4972d are not mounted c2, c14 and r8. application note 22/47 figure 34: component layout of fig. 33 (1:1 scale). evaluation board figure 35: p.c. board and component layout of the ciruit of fig. 33. (1: scale) application note 23/47 figure 36: test and evaluation board circuit. typical performances (using evaluation board) : n = 83% (v i = 35v ; v o =v ref ;i o = 3.5a ; f sw = 100khz) v o ripple = 30mv (at 1a) line regulation = 12mv (v i = 15 to 50v) load regulation = 7mv (i o = 0.5 to 3.5a) for component values refer to the fig. 35 (part list). part list r 1 = 30k w r 2 = 10k w r 3 = 15k w r 4 = 30k w r 5 =22 w r 6 = 4.7k w r 7 = see table a r 8 = option *c 1 =c 2 = 1000 m f 63v eyf (roe) c 3 =c 4 =c 5 =c 6 = 2,2 m f 50v c 7 = 390pf film c 8 = 22nf mkt 1837 (ero) c 9 = 2.7nf kp 1830 (ero) c 10 = 0.33 m f film c 11 = 1nf ** c 12 =c 13 =c 14 = 100 m f 40v ekr (roe) c 15 =1 m f film d1 = sb 560 (or equivalent) l1 = 150 m h core 58310 magnetics 45 turns 0.91mm (awg 19) cogema 949181 * 2 capacitors in parallel to increase input rms current capability. * * 3 capacitors in parallel to reduce total output esr. table b suggested boostrap capacitors operating frequency boostrap cap.c10 f = 20khz 680nf f = 50khz 470nf f = 100khz 330nf f = 200khz 220nf f = 500khz 100nf table a. v0 r10 r8 12v 15v 18v 24v 4.7k w 4.7k w 4.7k w 4.7k w 6.2k w 9.1k w 12k w 18k w note: in the test and application circuit for l4972d are not mounted c2, c14 and r8. application note 24/47 figure 37: component layout of fig. 36 (1:1 scale). evaluation board figure 38: p.c. board and component layout of the ciruit of fig. 36. (1: scale) application note 25/47 figure 39: test and evaluation board circuit typical performances (using evaluation board) : n = 83% (v i = 35v ; v o =v ref ;i o =5a;f sw = 200khz) v o ripple = 30mv (at 10a) with output filter capacitor esr 60m w line regulation = 5mv (v i = 15 to 50v) load regulation = 15mv (i o = 2 to 5a) for component values, refer to test circuit part list. parts list r 1 = 30k w c 1 ,c 2 = 3300 m f 63v l eyf (roe r 2 = 10k w c 3 ,c 4 ,c 5 ,c 6 = 2.2 m f r 3 = 15k w c 7 = 390pf film r 4 = 16k w c 8 = 22nf mkt 1817 (ero) r 5 =22 w 0,5w r 6 = 4k7 c 9 = 2.2nf kp1830 r 7 =10 w c 10 = 220nf mkt r 8 = see tab. a c 11 = 2.2nf mp1830 r 9 = option **c 12 ,c 13 ,c 14 = 220 m f 40v l ekr r 10 = 4k7 c 15 =1 m f film r 11 =10 w d1 = mbr 760ct (or 7.5a/60v or equivalent) l1 = 80 m h core 58930 magnetics 47 turns 113mm (awg 76) cogema 949178 * 2 capacitors in parallel to increase input rms current capability ** 3 capacitors in parallel to reduce total output esr table b suggested bootstrap capacitors operating frequency bootstrap cap.c10 f = 20khz 680nf f = 50khz 470nf f = 100khz 330nf f = 200khz 220nf f = 500khz 100nf table a. v0 r10 r8 12v 15v 18v 24v 4.7k w 4.7k w 4.7k w 4.7k w 6.2k w 9.1k w 12k w 18k w application note 26/47 figure 40: p.c. board (component side) and components layout of figure 39. (1:1 scale). figure 41: p.c. board (back side) and components layout of the circuit of fig. 39. (1:1 scale) application note 27/47 figure 42: test and evaluation board circuit typical performances (using evaluation board) : n = 83% (v i = 35v ; v o =v ref ;i o =7a;f sw = 200khz) v o ripple = 30mv (at 7a) with output filter capacitor esr 60m w line regulation = 5mv (v i = 15 to 50v) load regulation = 15mv (i o = 2 to 7a) for component values, refer to test circuit part list. parts list r 1 = 30k w c 1 ,c 2 = 3300 m f 63v l eyf (roe r 2 = 10k w c 3 ,c 4 ,c 5 ,c 6 = 2.2 m f r 3 = 15k w c 7 = 390pf film r 4 = 16k w c 8 = 22nf mkt 1817 (ero) r 5 =22 w 0,5w r 6 = 4k7 c 9 = 2.2nf kp1830 r 7 =10 w c 10 = 220nf mkt r 8 = see tab. a c 11 = 2.2nf mp1830 r 9 = option **c 12 ,c 13 ,c 14 = 220 m f 40v l ekr r 10 = 4k7 c 15 =1 m f film r 11 =10 w d1 = mbr 1560ct (or 16a/60v or equivalent) l1 = 40 m h core 58071 magnetics 27 turns 1,3mm (awg 16) cogema 949178 * 2 capacitors in parallel to increase input rms current capability ** 3 capacitors in parallel to reduce total output esr table b suggested bootstrap capacitors operating frequency bootstrap cap.c10 f = 20khz 680nf f = 50khz 470nf f = 100khz 330nf f = 200khz 220nf f = 500khz 100nf table a. v0 r10 r8 12v 15v 18v 24v 4.7k w 4.7k w 4.7k w 4.7k w 6.2k w 9.1k w 12k w 18k w application note 28/47 figure 43: p.c. board (back side) and components layout of the circuit of fig. 42. (1:1 scale) figure 44: p.c. board (back side) and components layout of the circuit of fig. 42. (1:1 scale) application note 29/47 resistors value for standard output voltages. vo (v) rx (k w ) ry (k w ) 12 15 18 24 4.7 4.7 4.7 4.7 6.2 9.1 12 18 rx corresponds to r9 for l4974a and l4972a ry corresponds to r10 for l4970a, l4977a and l4975a rx corresponds to r7 for l4974a and l4972a ry corresponds to r8 for l4970a, l4977a and l4975a the suggested switching frequency, and used in the dynamic tests, is 200khz for the multiwatt ? package (mw) and 100khz for the powerdip plastic package (pdip). the maximum switching frequency allowed is 500khz. for the types in plastic package (powerdip), the lower switching frequency suggested is only de- pended by the minor dissipating power of a plas- tic package versus a opower packageo because it is well known that switching losses are directly proportional to the commutation frequency. higher switching frequencies are possible if lim- ited output current is required and the operating ambient temperature are lower than 70 o c. infact the oscillator of the devices assembled in dual in line is completely equivalent to multiwatt ? pack- age. the most important external components which need a little more attention (because a properly dimensioning affects on the performance of the application) are the input and output capacitors, the freewheeling diode and the coil. input output capacitors the output voltage ripple d vo, essentially de- pends on the current ripple in the coil and the esr of the output capacitor at the switching fre- quency. the capacitor that present a low esr are capable of supporting higher current ripples. today, the majority of the constructors of elec- trolithic capacitors offer in their data book also a wide range of olow esro types generally sug- gested for switching power supply application. in our case ekr and eke series (roe) has been preferred. figure 45: oscillator waveform and sync. pulse for v i = 35v figure 46: oscillator waveform and sync. pulse for v i = 15v figure 47: oscilloscope photograph showing the short circuit output voltage and current waveforms. 10 m s/d 10w/div 5a/div 1 m s/div 1v/div 1 m s/div 1v/div application note 30/47 such a series capacitors are designed for appli- cations at high frequency, 200khz, and built to have a low esr in order of supporting high cur- rent ripple. in order to minimize the effects caused by the esr of the capacitors on the output voltage ripple 3 capacitors of 220uf/40v (for high output current application) are connected in parallel. it is necessary much attention also into the choice input capacitors. also them be at low esr, be- cause they must sustain high current ripples. such current ripples in presents of an inadeguate esr, would produce a heating of the capacitor it- self (which could affect on the reliability of the component, since in general it is sensitive to tem- perature. therefore choosing input capacitor at low esr is necessary for problems of reliability. in fact such capacitors, when used in applica- tions that make use a mains transformer, must support quite elevated peak current for short peri- ods a double the mains frequency and the same time be capable to deliver the instantaneous peak of energy to the load at the switching frequency. some other considerations of a general nature can be done on low esr capacitors. for example of equal value and type (i.e.: 220 m f - ekr), the esr of the capacitor decreases at the increasing of its value voltage rating, just like its rms cur- rent. still, two capacitors of the same value, connected in parallel, withstand an rms current higher then the only one of double value, and with the same voltage rating. when however, more capacitors are connected together in parallel, it is important to design with care the layout of the printed circuit, in order to distribute as eventy as possible amongst between the different capacitors the total current ripple. this is used to avoid dangerous current unbal- ances in the distribution of the total current be- tween the various capacitors charging some more others, that could damage the reliability of the system. often it is very difficult to know exactly the rms current flowing throught the capacitors. to know if the operating condition is a osafeooperating condi- tion or not, a measurement of the package tem- perature of the capacitor should be done. the following table 1 and 2, included in the dat- abook of electrical roederstain, shows the maxi- mum rms current sustainable by the ekr and eke capacitor versus the ambient temeperature and overtemperature allowed on the capacitor package. table 1. low-voltage electrolytic capacitors for switch-mode power supplies with low impedance values, radial, polarized styles. (ekr) rated cap. ( m f) rated volt. (v dc) dimensions d x l (mm) (nominal dimensions) dissipation factor tan d (100hz; 20 c) lim. values impedance z( w ) (10khz; 20 c) (lim. values) impedance z( w ) (10khz; 20 c) (lim. values) admissible ripple curr. (ma/100hz) 85 c admissible ripple curr. (ma/ eff /10- 100hz) 85 c 100 220 470 10 10 10 8.7 x 12.7 10 x 12.7 10 x 20 0.12 0.12 0.12 0.85 0.39 0.20 0.65 0.31 0.18 160 300 530 250 450 800 100 220 470 16 16 16 10 x 12.7 10 x 16 12.5 x 20 0.11 0.11 0.11 0.60 0.32 0.16 0.40 0.25 0.13 200 350 600 300 550 900 100 220 470 25 25 25 10 x 12.7 10 x 16 12.5 x 20 0.09 0.09 0.09 0.5 0.25 0.13 0.35 0.17 0.09 250 450 650 400 700 1000 100 220 470 40 40 40 10 x 16 12.5 x 20 12.5 x 30 0.08 0.08 0.08 0.4 0.17 0.09 0.23 0.13 0.08 450 650 1000 700 1000 1500 application note 31/47 (eke) rated cap. ( m f) rated volt. (v) dimensions d x l (mm) (nominal dimensions) dissipation factor tan d (100hz; 20 c) lim. values impedance z( w ) (100khz; 20 c) (lim. values) impedance z( w ) (100khz; -10 c) (lim. values) impedance z( w ) (10khz; -40 c) (lim. values) admissible ripple curr. (ma)100hz 105 c 22 33 47 100 220 330 330 470 10 10 10 10 10 10 10 10 5x11 5x11 5x11 5x11 6.3 x 11 8 x 11.5 8.5 x 12.5 8 x 11.5 0.19 0.19 0.19 0.19 0.19 0.19 0.19 0.19 1.30 1.30 1.30 1.30 0.60 0.33 0.33 0.33 3.90 3.90 3.90 3.90 1.80 0.99 0.99 0.99 20 20 20 20 9.80 5.80 5.80 5.80 154 154 154 154 260 400 400 400 100 220 220 330 470 16 16 16 16 16 6.3 x 11 8 x 11.5 8.5 x 12.5 8 x 11.5 10 x 12.5 0.16 0.16 0.16 0.16 0.16 0.60 0.33 0.33 0.33 0.25 1.80 0.99 0.99 0.99 0.75 9.80 5.80 5.80 5.80 3.20 260 400 400 400 510 100 220 330 470 25 25 25 25 6.3 x 11 8 x 11.5 10 x 12.5 10 x 16 0.14 0.14 0.14 0.14 0.60 0.33 0.25 0.19 1.80 0.99 0.75 0.57 9.80 5.80 3.20 2.20 260 400 510 635 100 100 220 330 470 35 35 35 35 35 8 x 11.5 8.5 x 12.5 10 x 12.5 10 x 16 10 x 20 0.12 0.12 0.12 0.12 0.12 0.33 0.33 0.25 0.19 0.14 0.99 0.99 0.75 0.57 0.42 5.80 5.80 3.20 2.20 1.50 400 400 510 635 860 table 2: admissible ripple current. ambient temp. d u in c admissible % of the 85 c value surface temp. in c admissible % of the 105 c value surface temp. in c 40 220 % 55 230 % 55 45 210 % 59 220 % 60 50 200 % 63 210 % 64 55 190 % 67 200 % 68 60 180 % 70 190 % 72 65 170 % 74 180 % 76 70 155 % 77 170 % 80 75 140 % 81 160 % 84 80 120 % 84 150 % 88 85 100 % 88 140 % 92 90 90 % 92 130 % 96 95 80 % 97 120 % 100 100 70 % 101 110 % 104 105 60 % 106 100 % 108 application note 32/47 catch diode because of quickly rise and fall time of the cur- rent (about 40-50ns) the use schottky diode is reccomanded. ultra-fast diodes with 30-50ns of trr (reverse recovery time) are not considered suf- ficiently fast for this family of converters, since they would give too elevated peaks of current at the turn on of the internal power transistor, so high thatcould affect the reliability of the complete system, as well as drastically reduce the effi- ciency. the oscilloscope photographs show the output voltage and output current waveforms obtained with diode having different trr value. in the test circuits used for this family of convert- ers, schottky diodes from 60v (breakdown re- verse voltage) are suggested since the device can support a max. input power voltage of 55v (for specific applications, schottky diodes with a reverse breakdown voltage higher or equal to the maximum supply voltage should be used), with current rating and packaging to satisfy all the con- ditions of duty cycle, and therefore also of power dissipation. coil concerning the coil, a molypermalloy toroidal cores has been suggested, so that it would be easy for everybody to obtain samples, wrap them with a right number of turns in order to evaluate and correlate the measurements and perform- ance of the devices. in addition since the devices are dynamically tested 100% in production, with a ojigo of testing which uses the same coil suggested in the appli- cations, in the case of contests for example on a guaranteed parameter like the efficiency, should be easier to solve the objections; in this case should be remembered that changing the mag- netic material, the dimension, the wire and the number of the winding, also change the losses in the coil reducing the total efficiency of the applica- tion. this can be easily verify using for example toroi- dal cores in iron powered rather that those sug- gested in molypermalloy. moreover, it is important to dimension properly the coil in order to avoid its saturation, a good choice is to dimension that its saturation; current is not equal to the maximum nominal current ca- pable to deliver to the load, but rather higher by about 20% then the maximum guaranted current of the device, in short circuit condition. only in this way it is possible to guarantee that the coil never saturate in all the possible working conditions, i.e.: in presence of a load transient, in short circuit in output and in the case of elevated temperature of the magnetic part. at last, it should be remembered that the sug- gested inductors values, are referred to the induc- tors values that the coil must have at the maxi- mum output current of the application. oscilloscope photographs showing the device output voltage and current waveforms obtained with different inductor. figure 48: schottky diode. figure 49: ultra fast diode (trr < 100ns). 10v/div 1a/div 1 m s/div 10v/div 1a/div 1 m s/div figure 50: waveforms for l = 50 m h 10v/div 1a/div 1 m s/div application note 33/47 anyway some general rules should be observed in order to avoid any opoor functioningo. these rules include: a) the catch diode, that further to be the sug- gested type in the test circuit, it has to be as- sembled on the printed circuit very close to the output of the regulator, in order to mini- mize the leakage inductance and avoid over voltage due to the long connection: b) the inductor, avoiding the saturation at the maximum current guaranted by the current limitation of the device. if oscillations on the output voltage at low ambient temperature (i.e.: below 0 o c) are originated an output low esr capacitor has to be used. oscillations on the output al low frequency indi- cate instability of the control loop; in this case a changing of the network compensation is sug- gested (see error amplifier section). low cost application the fig. 53 shows the low cost application of a power supply of 10a and 5.1v. in comparison of the complete application (and this is valid for all the devices of the family) the external components relative to the reset and power fail functions can be missed. when a lower output voltage ripple is not required it is possible to eliminate the capacitors con- nected at the reference voltage pin of 5.1v (i.e.: pin 14 for multiwatt package. pin 13 for plastic package) the reset input pin is suggested to connect it to ground. the soft start capacitor value can be reduced to 100nf for 5v output voltage. figure 51 : waveforms for l = 230 m h figure 52 : waveforms in case of core saturation 10v/div 1a/div 1 m s/div 10v/div 1a/div 1 m s/div figure 53: low cost application circuit. application note 34/47 power supply complete with mains transformer the fig. 54 shown a power supply with mains 110/220vac transformer, diode bridge and filter capacitor with output voltage adjustable between 5.1v. and 24v. output capacitors have to be chosen with low esr in order to reduce the output ripple.particular care has to be taken for input filter capacitors, in fact they have to support high current spikes at mains frequency and at the same time current peak bigger than the output current at the switch- ing frequency. therefore they must be chosen with low esr and able to substain high current ripple in order to guarantee a good reliability to all the system. the trasformer can be chosen with a single winding and 4 diodes or a center tap with only 2 diodes with higher reverse voltage. a cost reduction of the trasformer can be reached using an active power factor corrector. it work at low voltage and the external compo- nents are relatively cheap, more details can be obtained looking on the power factor corrector ap- plication note. power supply with mains high fre- quency preregulator. when it is necessary to eliminate the mains tras- former at 50/60hz for reasons like weight, dimen- sions or cost, a high frequency preregulator can be used. a ferrite trasformer reduces the rectifier and fil- tered mains voltage in a convenient voltage to supply directly the device, providing for the isola- tion requirements. using a free running solution or one of the volt- age/current mode controller available, it is possi- ble to compensate the input variation while the output voltage variations due to the load are usu- ally very low. some examples regarding how to use this regulator in off-line power supply are now showed: flyback topology using a flyback topology with single or double transistors is possible to fix a single output volt- age of 35-40v; it can be a bit increased if using a backup battery of 48 nominal volts. from this preregulator ( 10%) tolerancevoltage is possible to get one or more indipendent out- puts, with its own current limitation and thermal protection. moreover a possibility to syncronize more de- vices together is available, remembering to fix the master frequency at least 5% higher than the oth- ers device (working as slave) one. in case of necessity is possible to synronize de- vices on the trasformer secondary with the swith- cing frequency of the controller (see fig. 55). figure 54: typical power supply showing the mains transformer. application note 35/47 forward topology further is showed an smps forward circuit, where the dc-dc converter is used as post-regulator for an auxiliary output, (35v.) while the main one (5.1v. or 3.3v) is controlled directly with the feed- back (see fig. 56). using a pfc preregulation when an optimized power factor is required it is possible to use the following two pricinple dia- gram that make use of an active power factor cor- rector. 1) using the standard boost topology (fig. 57) 2) using a flyback topology (fig. 58) the idea is that to generate a stabilized voltage, around 30v - 35v, already isolated, avoiding to use an isolation after the pfc section. figure 55. figure 56. application note 36/47 power supply with 0 to 25v adjust- able output voltage a) it is a classical solution with high performance that make use of a negative reference voltage equal to the value of the internal voltage of the device (5.1v). to generate this negative reference voltage, it is useful to equip the mains trnsformer with another secondary winding at a low voltage of around 8vac and capable of delivering a few dozen of ma. during the phase of starting up and stopping of the mains, it is important to avoid generating os- cillations around the value of the output voltage , including the zero voltage. for this reason a network consisting of two npn signal transistors tr1 and tr2 and some resis- tors has been introduced. the transistor tr2 remains is saturation when tr1 is off, untill the output voltage of the negative regulator reaches 4.3v at this point tr1 goes in saturation, sending off tr2. in this way the soft start is blocked and the device begins to work starting in soft start. switching off the mains voltage, the regulator generating the negative volatge is still in regula- tion when the input voltage of the switching con- verter has already dropped below the turn on threshold. carefull attention must be given therefore to cal- culate the input capacitor of the two sections in order to avoid possible malfunctioning during the turning on and turning off. b) a solution that presents a cheaper costs and tha doesn't use a negative reference voltage is the following: setting the cursor opo to the adjustable resistance at 0v, using r1 and r2 the maximum output volt- age can be fixed. in this case we set r1 = 24kohm and r2 = 4k7ohm. in r1 the maximum flowing current will be limited at 1ma; with 1ma flowing in r1, vo = 30v. now by reducing the current in r1 the output volt- age vo can be adjusted till to 0v. figure 58. figure 57. application note 37/47 the current, flowing in backward, to have 0v it will be: i1 = v ref r1 = 5.1v 24k = 0.21ma d v r2 =r2 ? 0.21 = 4.7k ? 0.21 = 1v therefore, when the cursor opo reaches vref + 1v the output voltage goes to zero. at this point we are able to define as well the val- ues of p1 and r3. when the opo cursor is completely moved to high, there should be 6v of dropping to opo, and in this way 0.6ma will flow. the current flowing in r3, considering that the voltage at pin 15 has a typical value of 12v, it will be of 0.8ma. in this case the r3 value will be 7k5ohm. 3.3v / 10a dc-dc converter when an output voltage lower to the reference voltage of 5.1v must be stabilized with a good re- sult from stability and regulation point of view, and figure 59: 10a switching regulator, adjustable from 0v to 25v figure 60. application note 38/47 not having available the not-inverting input of the error amplifier, it is possible to use an external reference. in this case a tl431c reference has been cho- sen, which is cheaper and widespread used. in this case more than a simple reference, it is a true shunt regulator, containing a reference, an error amplifier and a transistor capable of absorb- ing a max current of 100ma. such component can be compensated like a common op/amp, and therefore in our applica- tion can substitute both the internal reference and the error amplifier. the fig. 61 represents the electrical diagram of the application at 3.3v. the operating input voltage is between 12v (due to the internal uvlo) and 35v, with a minimum operating switching frequency of 100khz. the maximum operating input voltage is limited only 35v because the minimum oono time, which should not be reduced below 1 microsecond. at input voltage of 35v, output voltage of 3.3v and fs=100khz the ton time is already about of 1 microsecond. infact we have: v o = v i t on t therefore: t on = v o v i t the inductor can be calculated using the usual formula, that is: l= ( v i - v o ) ? v o v i ? d i l ? fsw with d i l = 10% i omax ,l=30 m h when one operates with input voltage below of 5v, it' very difficult to obtain a good efficiency. in our case having the conduction losses and switching losses of the internal power transistor fixed by both external operating electrical condi- tion and the electrical characteristics of the itself power transistor, since integrate, it's necessary to optimize the losses of the catch diode, using new type at lower forward voltage drop, as soon as available on the market or by appropriately over- dimensioning. in some case a power mos used as a synchro- nouos switch can contribute to elevate the overall efficiency of the system. following are citated the principle results ob- tained by using our evaluation board: the same solution, obviously can be applied also to the other types of the family, adjusting if needed the compensation network and the coil. 2.2 m f l4970a 3 11 8 2.2 m f 36k 2.2nf 1 2 14 15 22k tl431 1k 0.1 m f 10 7 330 w 1k stps 1545 0.22 m f 6 9 50 m h ekr 1000 m f 10v vo=3.3v i o=10a 2200 m f 12v in this paragraph some suggestions will be given for how to abtain generators of constant current, more or less sophisticated according to the need. the examples given are time by time applicable to the different devices of this family of regulators, with the necessary adjustement according to the current required by the application. the diagram of fig. 66 propose a simple solution that makes use of two esternal small signal-tran- sistor best if matched in vbe, and some other passive components. for a cost reduction q1 can be substitute by a simple diode 1n4148. the divider composed by r2 and r1 fixes a volt- age at the whished voltage value (for example 50 -100mv) on the q2 emitter. q2 will be reversed bias untill the emitter voltage of q1 will raech the same value as itself. at this point q2 will be direct bias and will begin to absorb current from its collector; in the moment in which q2 will enter into conduction, a variation /\vsc at the current sense resistor will give a vari- ation of the q2 current equal to: d i cq2 = d v sc r1 when the current absorbed by q2 will reach the maximum current delivered by the error amplifier output (or by the current of the soft-start if this pin is prefered to use), the error amplifier will fall out of regulation and its output voltage will begin to decrease reducing, conseguentely, the duty cy- cle; then the regulator will begin in this way to be- have as a generator of current instead of voltage. the emitter voltage of q2 is fixed by the following formula: v eq2 = v ref r1 + r2 r1 = 5.1v r1 r1 + r2 a general criterium, is that of fixing the divider or1r2o in such way as to make a current flow that is greater than the necessary lowering the output voltage of the error amplifier. the maximum current delivered by the output of the transconduttance error amplifier is 200 m a; the current that has to flow in the divider r1r2 should be around of 2-3ma to have a very precise inter- vation or around only 1ma for slightly more soft interventions. by varying the value of r2, the point of interven- tion of the current limitation will be moved. the resistor rx contributes to introducing a more or less accentuate foldback effect, on the output current. in the following table suggest a few values of rsense according to the nax output current. r sense (m w )i o (a) device 10 15 30 50 100 10 7 5 3.5 2 l4970a l4977a l4975a l4974a l4972a the criterium used to defined the value of the sense resistor is essentially tied to the max power dissipated by the resistance, as well as to the market availability. if the mains objective is to maximize the efficiency output stage pwm e/a + - 5.1 2 1 10 15 14 8 l4972a/74a 6 11 9 lm358 + - 100nf 100 4.7k 100 rs v+ iomax= v+ rs v+= 5.1 100 100+4.7k ~100mv d93in004 figure 66. application note 41/47 when (delivering for example 10a), it is conven- ient to use two current transformers instead of a dissipative resistor, one in series to the source of the internal dmos and one in series to the catch diode. using such solution, a quite simple and fine regu- lation of the current is possible to implement. figure 66 shows a current generator solution with high precision on the current, using an op/amp in- stead of two small signal transistors. higher input voltage. since the maximum operating input voltage of this family is 50v, when one of these devices must be supplied with more elevated voltages, it is neces- sary to introduce a preregulator. fixing the output voltage of the preregulator of 45v, the power dissipation of the preregulator is: p d =i i ? v ce ? =i i ? (v i - 45) in the buck converter, the average input current is: i i = i o ? t on t = i o ? v o v i design example for l4974a (a) (b) vo = 5.1v io = 3.5a po = 17.85w vo = 12v io = 3.5a po = 42w ii = 0.388a ii = 0.933a with an operating input voltage of 60v the preregula- tor will dissipate: pd = 5.82w pd =13.4w the overall efficiency will be: n = 68% n = 70% up down converter in some applications it is required to stabilize a voltage starting from an input voltage which can be lower or higher then the output regulated volt- age. in this case a well known buck-boost topology is suggested. the fig. 68 which shows the electrical diagram of the up-down converter, makes use of the l4974a to generate an output voltage of 12v at 3a. for output current lower or higher than 3a other devices of this family can be used. for input volt- age less than 20v the zener diode can be avoided. such circuit can also be used as a simple step- up. in this case there is a structure of the oasym- metrical two transistor convertero type, that in the case of a short circuit is automatically protected since the internal transistor turn-off, disconnecting the power supply. this doesn't happen in the classical step-up con- verter topology, in which, during the short circuit only the power transistor is protected, but the cur- rent in the coil and the freewheeling diode is not limited. negative output voltage often it becomes necessary, in the multioutput power supplies, to generate negative voltages with current higher than 1a maintaining an ele- vated efficiency of the system. such outputs must have a good precision and stability and must be protected from short circuit- ing. with the application circuit suggested below, one the aime is to satisfy the performance listed above, and to contributing to the simplification of 2.7nf l4974a 11 30k 2.2 m f 17 8185 15k 22nf 20 sb560 220nf 1 150 m h 3x 100 m f ekr 2200 m f vi=50 to 70v d93in005 bdw23c 3k 10 m f 47v 3300 m f 50v 7 390pf vo=5v 9 figure 67: design example for l4974a application note 42/47 the power trasformer, both at 50hz and at high frequency. it's important to remember not to exceed the ab- solute maximum voltage ratings of the device. in this case the differential voltage applied to the de- vice is the sum of the maximum input voltage (positive) and of that controlled output negative. linear low drop post regulation in some application it becomes necessary to gen- erate stable, precise fixed or adjustable output voltages at high efficiency and with a truly negli- gible output ripple. summarizing a regulator that offers the quality of a linear type of control with the efficiency of a switching regulator. the fig. 70 shows the diagram of a swithcing preregulator at high efficiency followed by one or more series regulators of the type very olow dropo, or in the case of elevated current, by a discret low drop so- lution. 2.7nf l4974a 11 30k 2.2 m f 17 818 5,6 15,16 15k 22nf 20 sb560 220nf 1 100 m h 470 m f 1000 m f 12v but since the aim of this section is not that of studing the transistors, the circuit can be further reduced as shown in figure 74. if we now consider the ground potential as ambi- ent temperature, we have: t j =t a +(r jc +r th )p d a) r th = t j - t a - r jc p d p d b) t c =t a +r th pd c) thermal contact resistance depends on various factors such as the mounting, contact area and planarity of the heatsink. with no material be- tween the device and heatsink the thermal resis- tance is around 0.5 c/w;; with silicone grease roughly 0.3 c/w and with silicone grease plus a mica insulator about 0.4 c/w. see fig. 75. in ap- plication where one external transistor is used to- gether, the dissipated power must be calculated for each component. the various junction tem- perature can be calculated by solving the circuit shown in fig. 75. this applies if the dissipating elements are fairly close with respect to the dissi- pator dimensions, otherwise the dissipator can no longer be considered as a concentrated constant and the calculation becomes difficult. this con- cept is better explained by the graph in fig.77 which shows the case (and therefore junction) temperature variation as a function of the dis- tance between two dissipating elements with the same type of heatsink and the same dissipated power. the graph in fig. 77 refers to specific case of two elements dissipating the same power, fixed on a rectangular aluminium plate with a ratio of 3 between the two sides. the temperature jump will depend on the total dissipated power and on the devices geometrical positions. we want to show that there exists an optimal position between the two devices: d = 1 2 ? side of the plate figure 71. figure 72. figure 73. figure 74. figure 75. figure 76. application note 45/47 fig. 78 shows the trend of the temperature as a function of the distance between two dissipating elements whose dissipated power is fairly differ- ent (ratio 1 to 4). this graph may be useful in ap- plications with two devices in mtw package are synchronized. references: 1) an244 odesigning with the l296 monolithic power switching regulatoro (ref. designer' guide to power products application manual). 2) table1 (see page 31-32/46) ekr & eke roederstein low voltage electrolytic capaci- tors. figure 77. figure 78. application note 46/47 information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs- thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1997 sgs-thomson microelectronics printed in italy all rights reserved sgs-thomson microelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. application note 47/47 |
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